This invention relates to an amplifier device such as an amplifier circuit or a buffer circuit, etc. capable of performing an efficient amplifying operation even by a low power consumption, and more particularly to an amplifier device for driving capacitive load, etc. such as, for example, an image display, etc. using a liquid crystal panel.
For the amplifier, the slew rate is one of the significant factors determining the performance of the circuit. Namely, it is very important to provide a high slew rate for the amplifier. While the slew rate can be improved by increasing a bias current delivered to the amplifier stage, the power consumption increases accordingly if a bias current is caused to be increased. Thus, various attempts have been conventionally made in order to solve this problem.
For the amplifier for driving a capacitive load, etc., there are two kinds of amplifiers: one is directed to a signal sampled in time and subject to level changes every fixed period in a switched capacitor network, etc.; the other is directed to a signal completely non-periodically subject to level changes.
For the prior art related to the amplifier of the former type, on pp. 257 (final paragraph) to 259 of `Analog MOS Integrated Circuits For SIGNAL PROCESSING`, Roubik Gregorian, et al., John Wiley & Sons 1986, the operation of an operational amplifier having clock controlled bias means is described and the circuit diagrams thereof are shown in FIG. 4. 129 and FIG. 4 130.
In these conventional circuits, an approach is employed to control the bias current so that the output current driving capability is high at the beginning of the clock period and the operating current is equal to zero at the end of the clock period to increase the output current driving capability only when high response is required because there occurs changes in the signal level, and to allow the operating current to be equal to zero when there is no change in the signal level, thus to advantageously provide both the high slew rate and low power consumption.
However, the fact that the operating current is equal to zero when there is no change in the signal level implies that the output is in a high impedance state. Therefore, such conventional circuits are disadvantageously apt to undergo the influence of disturbance on the load side when the output level is in a high impedance state.
To avoid this drawback, there is proposed in U.S. Pat. No. 4,502,019 a system in which a constant current source is added to allow a small quantity of current to flow even when there is no change in the level of an input signal, thus preventing the output level from being brought into a high impedance state.
Further, an example of the conventional amplifiers similar to the above-mentioned prior art is shown in FIG. 1. This amplifier is provided for delivering a drive power to a liquid crystal panel 20 as a capacitive load, and includes a buffer section of the voltage-follower type using first and second amplifier circuits 21 and 22. The liquid crystal panel comprises a liquid crystal cell LC as a capacitive load, a MOS type transistor TFT, and a capacitor C100 of a signal line having a value of 40-200 pF. Further, the amplifier includes two switches SWc and SWd turned ON and OFF by an INH signal, and a capacitor C101 for storing a phase compensation capacitance. In addition, the above-mentioned amplifier circuit 22 includes a very small current source I0 and a MOS type transistor M220.
The operation of the amplifier shown in FIG. 1 will now be described. Immediately before an input signal shown in FIG. 2(c) varies, the switches SWc and SWd are closed by an INH signal (see FIG. 2(b)). As a result, the input terminal voltage and the output terminal voltage are once reset to VDD (FIG. 2(d)). Then, the switches SWc and SWd are opened by the INH signal in correspondence with the timing at which the input signal varies. Thus, the buffer section (amplifier circuits 21 and 22) is normally cased to be operative.
As described above, when the input and output terminal voltages are both once reset to VDD, the output voltage is dropped from VDD to a voltage following the input voltage, and is stabilized thereat. The slew rate at this time is determined by the phase compensation capacitance C101 and the output current of the first amplifier circuit 21. The reason therefor is that a sink current of the output transistor M220 of the second amplifier circuit 22 is determined by the gate voltage of the transistor M220. Accordingly, settling time required until the output voltage is brought into a stable state following the input can be shortened.
If the output voltage is not reset to VDD, the change in falling of the output voltage is the same as stated above, but the change in rising of the output voltage becomes dependent upon any slow one of the slew rate determined by the phase compensation capacitance C101 and the output current of the first amplifier circuit and the slew rate determined by the current source I0 of the second amplifier circuit 22 and the capacitance of a load connected to the output side of the current source I0. In order to allow the slew rate determined by the the current source I0 and the load capacitance to be high, it is required to set in advance the current of the current source I0. However, once the output is stabilized, all the currents from the current source I0 flow into the output transistor M220, and are uselessly consumed.
However, in accordance with the amplifier of FIG. 1, an instantaneous current flowing on the VDD line when the switches SWc and SWd are closed by the INH signal becomes extremely large. In an IC for driving a liquid display panel including a large number of buffer sections constructed as above, the power supply voltage undergoes the influence such as voltage drop, etc. based on the resistance component of the VDD line by that large instantaneous current, resulting in bad influence on the circuit operation of the amplifier. This is not preferable for insuring reliability.
Even if a circuit device is made as in disclosed in U.S. Pat. No. 4,502,019, in uses where many amplifiers are mounted on one chip to provide outputs at the same time, e.g., as in a drive IC of a liquid crystal display, an impulse like noise by the voltage drop of the power supply line inside and outside IC, etc. results because of a large instantaneous current at the beginning of the clock period. This results in an erroneous operation or deterioration in reliability due to migration on the power supply line, etc. inside the IC. This is disadvantageous to the implementation of an IC.
For the buffer circuit directed to a signal completely non-periodically subject to level changes, there have been conventionally proposed a variety of circuits which attempt to reduce current consumption. The following references provide examples: a circuit (first prior art embodiment) shown in FIG. 3 of `Class AB CMOS Operational Amplifier with Very High Efficiency`, L., Callewaert, Katholieke Uniivesiteit Leuven, Elec. Eng. Dept. Annual Report-1188; a circuit (second prior art embodiment) shown in FIG. 1 of `Low-Power High-Drive CMOS Operational Amplifiers`, V. R., Saari, IE3 ISSC vol SC-18, No. 1, Feb., 1983; and a circuit (third prior art embodiment) shown in FIG. 3 of `Adaptive Biasing CMOS Amplifiers`, M. G., Degrauweel IE 3 JSSC vol. SC-17, No. 3 June 1982.
These circuits are adapted to control the operating current in the circuit by the magnitude of the differential input amplitude or the magnitude of the differential amplitude in the amplifier. Namely, when the differential input amplitude is large, the output current driving capability is increased, while when the differential input is small, the driving capability is decreased. Thus, the power consumption is reduced.
However, in the case of the first and third prior art embodiment, the number of elements is considerably increased, resulting in large circuit scale. This is also disadvantageous to the implementation of an IC. Further, in the second prior art embodiment, because the number of capacitors is large, a large area is required when the circuit is constructed as an IC. This is also disadvantageous to the implementation of an IC.
As stated above, while the conventional amplifier can provide a high slew rate at a low power consumption, they have circuit configurations which are disadvantageous to the implementation of an IC.